1. Field of the Invention
The present invention relates to a liquid crystal display (LCD) device, and more particularly to an array substrate for an in-plane switching (IPS) mode LCD device and a fabricating method thereof.
2. Discussion of the Related Art
In general, an LCD device is driven using optical anisotropy and polarization of liquid crystal. The liquid crystal has a directivity in an arrangement of molecules due to its thin and long structure. The directivity of the arrangement of the liquid crystal molecules is controllable by applying an electric field to the liquid crystal.
When the direction of the arrangement of the liquid crystal molecules is voluntarily adjusted, the arrangement of the liquid crystal molecules changes, and light is refracted in the direction of the arrangement of the liquid crystal molecules by virtue of optical anisotropy of the liquid crystal, thereby displaying the image.
An Active Matrix (AM) LCD (AM-LCD, hereinafter, referred to as LCD device), in which thin film transistors (TFTs) and pixel electrodes connected to the TFTs are arranged in a matrix form, is known for its high resolution and superior video implementation capability.
The LCD device includes a color filter substrate (i.e., upper substrate) having common electrodes, an array substrate (i.e., lower substrate) having pixel electrodes, and a liquid crystal layer interposed between the upper and lower substrates. The LCD device having such structure is driven by vertical electric field created between the common electrodes and the pixel electrode. Accordingly, such structures have excellent properties such as transmittance, an aperture ratio, and the like.
However, such LCD devices have poor viewing angle properties. Thus, a newly introduced technique to overcome the drawback is a liquid crystal driving method using horizontal electric fields for the in-plane switching (IPS), which has improved viewing angle properties.
The IPS mode LCD device is configured to have the color filter substrate and the array substrate face each other, and have a liquid crystal layer interposed between the color filter substrate and the array substrate. The array substrate includes a TFT, a common electrode, and a pixel electrode located at each of a plurality of pixels defined on a transparent insulating substrate. The common electrode and the pixel electrode are spaced apart from each other in parallel on the same substrate. The color filter substrate includes black matrixes located in correspondence to positions of the gate line, the data line and the TFT all formed on the transparent insulating substrate, and a color filter located in accordance with a position of each pixel.
The liquid crystal layer is driven by horizontal fields between the common electrode and the pixel electrode. In the IPS mode LCD device having the structure, the common electrode and the pixel electrode are formed to be transparent to ensure luminance. However, end portions of the common electrode and the pixel electrode block light, thereby reducing the aperture ratio.
Hereinafter, description will be given to the structure of the array substrate for the related art IPS mode LCD device. FIG. 1 is a plane view of an array substrate for the related art IPS mode LCD device. FIG. 2 is a sectional view taken along the line III-III of FIG. 1, i.e., a sectional view of the array substrate for the IPS mode LCD device.
The array substrate for the related art IPS mode LCD device, as shown in FIGS. 1 and 2, includes a plurality of gate lines 13 and common lines 13b and 13c extending in one direction on a substrate 1 and spaced from each other in parallel, a plurality of data lines 21 intersecting with the gate lines 13 to define pixel regions at the intersections therebetween, a plurality of pixel electrodes 25a formed at the pixel regions defined by the gate lines 13 and the data lines 21, thin film transistors (TFTs) T disposed at the intersections of the gate lines 13 and the data lines 21. Each TFT T includes a gate electrode 13a, an active layer (not shown), a drain electrode 21b and a source electrode 21a, and common electrodes 25c disposed at the pixel regions defined by the gate lines 13 and the data lines 21, the common electrodes 25c being spaced apart from the pixel electrodes 25a. 
The gate line 13 provides a scan signal from a gate driver (not shown). The data line 21 provides a video signal from a data driver (not shown). A gate insulating layer 15 is interposed between the gate line 13 and the data line 21.
The common lines 13b and 13c are formed simultaneously when forming the gate lines 13. The common line 13b is arranged to be parallel to the gate line 13, and the common line 13c is arranged to be perpendicular to the gate line 13. The common lines 13b and 13c are connected to each other. The common line 13c overlaps with the data line 21 having the gate insulating layer 15 interposed therebetween.
The TFT T allows the pixel electrode 25a to be charged with a pixel signal applied to the data line 21 by a scan signal applied to the gate line 13 and remain in the signal-charged state. The TFT T includes a gate electrode 13a connected to the gate line 13, a source electrode 21a connected to the data line 21, a drain electrode 21b facing the source electrode 21a and connected to the pixel electrode 25a, an active layer 17 overlapping with the gate electrode 13a having the gate insulating layer 15 interposed therebetween to form a channel between the source electrode 21a and the drain electrode 21b, and an ohmic contact layer 19 formed on the active layer 17. The ohmic contact layer 19 is formed on regions of the active layer 17 excluding the channel region between the source and drain electrodes 21a and 21b. 
A plurality of transparent pixel electrodes 25a are disposed on the entire surface of the pixel region being spaced apart from the gate line 13 and the data line 21. The plurality of pixel electrodes 25a are electrically connected to the drain electrode 21b via a contact hole 23a formed through a lower passivation film 23. One end of the plurality of pixel electrodes 25a is connected together with a pixel electrode connection line 25b, which overlaps with the common line 13b. 
As shown in FIG. 1, end portions of the plurality of common electrodes 25c spaced apart from the pixel electrodes 25a are connected together with a common electrode connection line 25d. The common electrode connection line 25d is electrically connected to the common line 13c via the common line contact hole 23b. 
As shown in FIG. 2, in the structure of the array substrate for the related art LCD device, a first parasitic capacitor C1 is formed between the pixel electrode connection line 25b and the common line 13b with the gate insulating layer 15 and the passivation film 23 interposed therebetween, and a second parasitic capacitor C2 is formed between the drain electrode 21b and the common line 13b overlapping with the drain electrode 21b with the gate insulating layer 15 interposed therebetween.
The common electrodes 25c apply a reference voltage, i.e., a common voltage to each pixel in order to drive the liquid crystal. The pixel electrode 25a and the neighboring common electrodes 25c generate a horizontal field therebetween. Accordingly, when a video signal is applied to the pixel electrode 25a via the TFT T, the voltage difference between the pixel electrode 25a and the common electrodes 25c, to which a common voltage is applied, generates horizontal fields to rotate liquid crystal molecules arranged in a horizontal direction using dielectric anisotropy. The transmittance of light in the pixel region changes according to the rotation level of the liquid crystal molecules.
However, according to the related art, as shown in part “A” of FIG. 2, a first parasitic capacitor C1 is formed between the pixel electrode connection line 25b and the common line 13b, and a second parasitic capacitor C2 is formed between the drain electrode 21b and the common line 13b. The related art structure requires a space for forming such parasitic capacitors, which may cause an aperture ratio to be lowered accordingly. In particular, since the first and second parasitic capacitors C1 and C2 are formed horizontal rather than perpendicular to each other, they may occupy more area on the array substrate thereby lowering the aperture ratio accordingly.